diff options
| author | wires <wires@noreply.wires.systems> | 2025-10-06 06:07:10 -0400 |
|---|---|---|
| committer | wires <wires@noreply.wires.systems> | 2025-10-06 06:07:10 -0400 |
| commit | 2379c573da65fd13d4e5bd16619b321744ac37fe (patch) | |
| tree | 9552f19b902fe9626b6c9e644f131d7bad8bdd0e /src/mini_uart.zig | |
| parent | get building on 0.15.1 (diff) | |
| download | zosimos-2379c573da65fd13d4e5bd16619b321744ac37fe.tar.gz | |
blocking serial messages
Diffstat (limited to 'src/mini_uart.zig')
| -rw-r--r-- | src/mini_uart.zig | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/src/mini_uart.zig b/src/mini_uart.zig new file mode 100644 index 0000000..265268d --- /dev/null +++ b/src/mini_uart.zig @@ -0,0 +1,55 @@ +const std = @import("std"); + +const board = @import("board.zig"); +const AUX_BASE = board.AUX_BASE; +const AUX_ENABLE = board.AUX_ENABLE; + +const gpio = @import("gpio.zig"); +const mmio = @import("mmio.zig"); + +const IO = AUX_BASE + 0x40; +const IER = AUX_BASE + 0x44; +const IIR = AUX_BASE + 0x48; +const LCR = AUX_BASE + 0x4c; +const MCR = AUX_BASE + 0x50; +const LSR = AUX_BASE + 0x54; +const MSR = AUX_BASE + 0x58; +const SCRATCH = AUX_BASE + 0x5c; +const CNTL = AUX_BASE + 0x60; +const STAT = AUX_BASE + 0x64; +const BAUD = AUX_BASE + 0x68; + +pub fn enable() void { + board.enableAux(.mini_uart); + + gpio.setPull(14, .none); + gpio.setFunction(14, .alt5); + + gpio.setPull(15, .none); + gpio.setFunction(15, .alt5); + + mmio.write(IER, 0); // disable interrupts + mmio.write(IIR, 6); // clear FIFOs + mmio.write(LCR, 3); // 8 bit mode + mmio.write(BAUD, baudRegVal(115200)); + + mmio.write(CNTL, 0x3); +} + +fn baudRegVal(baud: comptime_int) comptime_int { + return 500000000 / (baud * 8) - 1; +} + +fn writeByte(b: u8) void { + while ((mmio.read(LSR) & 0x10) != 0) {} + mmio.write(IO, b); +} + +pub fn writeString(str: []const u8) void { + for (str) |b| { + if (b == '\n') { + writeByte('\r'); + } + writeByte(b); + } +} |